Ferventz Semiiconductor is hiring for the following positions
1) Senior Analog Layout Engineers
- 3+ years of experience in Analog
- Experience in Floor planning of block level layout and Chip level designs
- Experience in 14nm and below is a plus
- Performing layout verification checks like LVS/DRC, ERC
- Excellent in debugging skills.
- Basic understanding of CMOS circuit
2) Memory Layout Engineers
- 3+ years of experience in Memory layouts.
- Experience in Floor planning of block level layout and Chip level designs
- Performing layout verification checks like LVS/DRC, ERC
- Excellent in debugging skills.
- Experience in 14nm and below is plus.
- Basic understanding of CMOS circuit layout structures required
- Proficiency with Cadence Virtuoso and Calibre verification tools.
- Understanding of basic CMOS circuits is a plus.
3) Analog Circuit Designers
- Bachelors/Masters in CS/EE from a reputed university/institution.
- -2+ years of industry experience in related field.
- Good understanding of CMOS circuit design fundamentals, device physics, control & communication and transmission line theory.
- Should have experience starting from circuit specifications, can create simulation benches to verify the specification, can understand and debug circuit.
- Should have basic understanding of layout and parasitic extraction.
- Good exposure to spice simulations and various sub-micron design methodologies;
- Understanding of physical design and its impact on design, specifically in submicron nodes.
Send your application and resume to:
hr@ferventz.com
